In integrated circuit (IC) design, transistor performance and, particularly, field effect transistor (FET) performance can vary from a nominal performance as a function of the FET's proximity to certain adjacent features. This phenomenon is referred to as the local layout effect (LLE) and adjacent features that impact a FET's performance are referred to herein LLE-inducing features. Exemplary LLE-inducing features include, but are not limited to, strain-inducing features (i.e., features that impart strain on the channel region of the FET). Strain-inducing features can include, for example, stress layer(s), which are specifically incorporated into the design layout for the purpose of imparting strain in order to optimize FET performance. This technique is referred to as strain engineering. Such stress layer(s) can overlay the entire FET (i.e., can be stress overlayers), can be embedded within each of the source/drain regions of the FET (i.e., can be embedded stress layers), can be above each of the source/drain regions of the FET, etc. Other strain-inducing features can include, for example, isolation regions, spacers, other devices, or other structural components that are incorporated into the design layout for non-stress related purposes, but which by reason of their placement impart strain. Other LLE-inducing features can include features, such as well regions or other dopant implant regions, which exhibit dopant scattering. Still other LLE-inducing features include features that exhibit structural variations due to lithographic patterning variations (e.g., features that exhibit rounded corners as compared to squared corners indicated in the design layout because of variations that occur during lithographic patterning of the features). In any case, LLE-inducing features can alter model parameter(s) of the FET and can thereby alter performance attribute(s) of the FET. Exemplary model parameters that can vary due to LLEs include, but are not limited to, charge carrier mobility (u0), saturation threshold voltage (Vtsat), carrier saturation velocity, drain-induced barrier lowering (DIBL) and series resistance. Exemplary performance attributes that can vary as a function of variations in such model parameters can include, but are not limited to, effective drive current (Ieff), linear drain current (Idlin), and saturation drain current (Idsat). Since the LLE will vary as a function of the distance(s) between the LLE-inducing feature(s) and the FET, the model parameters for essentially identical FETs and, thereby the performance attributes associated with those FETs will vary as a function of FET placement within the design layout. Modeling the local layout effect (LLE) of a LLE-inducing feature on a performance attribute of a FET is complex and becomes even more complex when the LLE-inducing feature has a nonlinear edge (e.g., a serrated or jagged edge) such that different areas of the FET channel region are separated from the edge by different distances and, thereby such that the LLE across the FET channel region is non-uniform.